Comparator trees for winner-take-all circuits

David Cyril Hendry

Research output: Contribution to journalArticlepeer-review

16 Citations (Scopus)


This paper presents architectures for comparator trees capable of finding the minimum value of a large number of inputs. Such circuits are of general applicability although the intended application for which the circuits were designed is the winner-take-all function of a digital implementation of a neural network based on the self organising map. Mechanisms for reducing delay based on look-ahead logic within individual comparators and mechanisms based on multiplexor architectures of a comparator are compared for both propagation delay and area. (C) 2004 Elsevier B.V. All rights reserved.

Original languageEnglish
Pages (from-to)389-403
Number of pages14
Publication statusPublished - Dec 2004


  • self organising map
  • hardware implementations
  • winner-take-all
  • comparator trees


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