A fast simulation method for analysis of SEE in VLSI

Yufan Lu, Xin Chen, Xiaojun Zhai*, Sangeet Saha, Shoaib Ehsan, Jinya Su, Klaus McDonald-Maier

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)
4 Downloads (Pure)


The transistor simulation tools (e.g. TCAD and SPICE) are widely used to simulate single event effects (SEE) in industry. However, due to the variances of the physical parameters in practical design, e.g. the nature of the particle, linear energy transfer and circuit characteristics would have a large impacts on the final simulation accuracy, which will significantly increase the complexity and cost in the workflow of the transistor level simulation for large scale circuits. Therefore, a new SEE simulation scheme is proposed to offer a fast and costefficient method to evaluate and compare the performance of large scale circuits in the effects of radiation particles. In this work, we have combined both the advantages of transistor and hardware description language (HDL) simulations, and proposed accurate SEE digital error models for high-speed error analysis in the large scale circuits. The experimental results show that the proposed scheme is able to handle SEE simulations for more than 40 different circuits with the sizes varied from 100 transistors to 100 k transistors.

Original languageEnglish
Article number114110
Number of pages12
JournalMicroelectronics reliability
Early online date30 Mar 2021
Publication statusPublished - 1 May 2021

Bibliographical note

This work is supported by the UK Engineering and Physical Sciences Research Council through grants EP/R02572X/1 and EP/P017487/1.


  • Single event effect
  • Fault injection
  • SEE models
  • SEE mitigation
  • HDL simulation
  • VLSI


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